The present invention relates, in general, to the field of computer systems and methods incorporating one or more reconfigurable processing elements. More particularly, the present invention relates to a switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus (“RIMM”) format for a computing system employing multi-adaptive processing elements (“MAP®”, both trademarks of SRC Computers, Inc.) for use with interleaved memory controllers in order to provide enhanced data transfer rates.
Among the most currently promising methods of creating large processor count, cost-effective computers involves the clustering together of a number of relatively low cost microprocessor based boards such as those commonly found in personal computers (“PCs”). These various boards are then operated using available clustering software to enable them to execute, in unison, to solve one or more large problems. During this problem solving process, intermediate computational results are often shared between processor boards.
Utilizing currently available technology, this sharing must pass over the peripheral component interconnect (“PCI”) bus, which is the highest performance external interface bus, commonly found on today's PCs. While there are various versions of this bus available, all are limited to less than 1 GB/sec. bandwidth and, because of their location several levels of chips below the processor bus, they all exhibit a very high latency. In low cost PCs, this bus typically offers only on the order of 256 MB/sec. of bandwidth.
These factors, both individually and collectively can significantly limit the overall effectiveness of the cluster and, if a faster interface could be found, the ability of clusters to solve large problems would be greatly enhanced. Unfortunately, designing a new, dedicated chip set that could provide such a port is not only very expensive, it would also have to be customized for each type of clustering interconnect encountered. This would naturally lead to relatively low potential sale volumes for any one version of the chipset, thus rendering it cost ineffective.
With ever-increasing processor speeds, the need for high performance memory subsystems has also continued to increase. Since the development of the Switch/Network Adapter Port system as disclosed in the aforementioned U.S. patent application Ser. No. 09/932,330, the technology for high performance memory subsystems for the personal computer (“PC”) market has come to include the use of interleaved memory.
In an interleaved memory system, two or more dual in-line memory module (“DIMM”) slots are accessed by the memory controller at the same time. When a by-two interleaving scheme is used, the width of the data bus is effectively doubled, thus doubling the bandwidth that is obtained to memory. A similar configuration can be established to form a by-four, or four way, interleaved system using four DIMM slots. This form of memory controller is currently one of the more common high performance memories found in the higher end server systems and is rapidly becoming available in more mainstream products.